CMOS Drivers and Receivers Descriptions

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CMOS Drivers

N83X-AS
32 channel CMOS VCSEL driver with self-test (packaged) This VCSEL driver circuit designed in 0.5 m CMOS contains an adjustable on-chip clock generator and on-chip generation capabilities of a pseudo-random data stream for testing up to 500 MHz. It is based on the 10-Channel version.

N74K-AE
-10-channel CMOS VCSEL driver (packaged) This VCSEL driver circuit designed in 0.5 m CMOS contains an adjustable on-chip clock generator and on-chip generation capabilities of a pseudo-random data stream for testing up to 500 MHz. The circuit consists of two PMOS drain-shorted transistors that are designed to source current while operating in the saturation regime. One transistor supplies the modulation current, and the other supplies the bias current. Both modulation and bias are adjustable.

N84C-AG
- 8x8 VCSEL driver for flip-chip bonding (unpackaged) The VCSELs to be flip chip bonded should have 125 m pitch. The bond pads are Al as received from the fab and require preparation to connect to VCSELs. The circuit consists of two shunt-connected PMOS transistors, one of the PMOS transistors provides the quiescent current into the VCSEL and the other provides the modulated drive current. The quiescent current can be controlled by Vbias. The drivers were tested to data rates up to 1.2 Gbps (NRZ).

N73B-AC
16 Channel CMOS VCSEL driver with voltage adjust Packaged in 65-pin PGA, with pads for wire bonding, this circuit drives a VCSEL array. The driver fabricated in 0.8 m features consists of six n-MOS transistors in series. An adjustable external input (0-5 V) for the chip determines the bias current for the output current of the drivers. It is expected to operate from DC to above 100 Mbps (RZ) and 200 Mbps (NRZ).

CMOS Receivers

N73B-AB
16-channel CMOS transimpedance receiver (unpackaged) These are receiver circuits that are suitable for differential input devices, such as SEED, and require separate photodetectors. The 16 receiver inputs are to be connected to the outputs of differential photodetectors that provide at least mA of input current. The receiver design consists of a transimpedance amplifier consisting of an open loop gain (achieved by a CMOS inverter) and a feedback resistance (achieved by a p-MOS transistor). The transimpedance amplifier is followed by four inverting stages to bring the transimpedance amplifier output up to logic level voltages.

N89D-AC
4x4 GaAs receiver array (packaged) A 4x4 array of MSM detectors coupled to a receiver circuit and an output driver circuit to support 1 Gbps. The MSM photodetectors are 75 m diameter with 2.1 m finger spacings. The detectors are placed on a 250 m pitch. The array OEICs require +2V and +3.3V supplies in addition to a photodetector bias and a reference voltage. The receiver circuit utilizes three gain stages. The first stage consist of matched single-ended transimpedance amplifiers. The second stage consist of pairs of matched single-ended amplifiers. The third stage is a differential voltage amplifier and its balanced outputs are converted to an unbalanced signal which drives a DCFL inverter. A line driver is used to to deliver the DCFL output of the receiver to the ECL output drivers. Dedicated ECL outputs are provided for each of the 16 receivers.

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N83X-AS 32 channel CMOS VCSEL driver with self-test (packaged)	This VCSEL driver circuit designed in 0.5 m CMOS contains an adjustable on-chip clock generator and on-chip generation capabilities of a pseudo-random data stream for testing up to 500 MHz. It is based on the 10-Channel version.
N74K-AE -10-channel CMOS VCSEL driver (packaged)	This VCSEL driver circuit designed in 0.5 m CMOS contains an adjustable on-chip clock generator and on-chip generation capabilities of a pseudo-random data stream for testing up to 500 MHz. The circuit consists of two PMOS drain-shorted transistors that are designed to source current while operating in the saturation regime. One transistor supplies the modulation current, and the other supplies the bias current. Both modulation and bias are adjustable.
N84C-AG - 8x8 VCSEL driver for flip-chip bonding (unpackaged)	The VCSELs to be flip chip bonded should have 125 m pitch. The bond pads are Al as received from the fab and require preparation to connect to VCSELs. The circuit consists of two shunt-connected PMOS transistors, one of the PMOS transistors provides the quiescent current into the VCSEL and the other provides the modulated drive current. The quiescent current can be controlled by Vbias. The drivers were tested to data rates up to 1.2 Gbps (NRZ).
N73B-AC 16 Channel CMOS VCSEL driver with voltage adjust	Packaged in 65-pin PGA, with pads for wire bonding, this circuit drives a VCSEL array. The driver fabricated in 0.8 m features consists of six n-MOS transistors in series. An adjustable external input (0-5 V) for the chip determines the bias current for the output current of the drivers. It is expected to operate from DC to above 100 Mbps (RZ) and 200 Mbps (NRZ).